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Features
* High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 (nominal) * Up to 2.7 Million Used Gates and 976 Pins * System Level Integration Technology
- Cores: ARM7TDMITM and AVR(R) RISC Microcontrollers, OakDSPTM and LodeDSPCoresTM, 10T/100 Ethernet MAC, USB and PCI Cores - Memory: SRAM, ROM, CAM and FIFO; Gate Level or Embedded * I/O Interfaces; CMOS, LVTTL, LVDS, PCI, USB - Output Currents up to 20 mA, 5V Tolerant I/O * Deep Submicron CAD Flow
Description
The ATL35 Series Gate Array and Embedded Array families are fabricated on a 0.35 CMOS process with up to 4 levels of metal. This family features arrays with up to 2.7 million routable gates and 976 pins. The high density and high pin-count capabilities of the ATL35 family, coupled with the ability to embed microcontroller cores, DSP engines, and memory, all on the same silicon, make the ATL35 series of arrays an ideal choice for System Level Integration.
Gate Array/ Embedded Array ATL35 Series
ATL35 Array Organization
Device Number ATL35/44 ATL35/68 ATL35/84 ATL35/100 ATL35/120 ATL35/132 ATL35/144 ATL35/160 ATL35/184 ATL35/208 ATL35/228 ATL35/256 ATL35/304 ATL35/352 ATL35/388 ATL35/432 ATL35/484 ATL35/540 ATL35/600 ATL35/700 ATL35/800 ATL35/900 ATL35/976 Notes: 4LM Routable Gates(1) 4,195 13,230 22,200 33,480 47,839 59,185 71,737 90,514 121,877 150,085 182,880 233,774 334,044 425,958 520,695 652,421 768,033 964,078 1,196,371 1,642,242 1,999,526 2,542,995 2,767,931 3LM Routable Gates(1) 3,729 11,760 19,734 29,760 42,211 52,222 63,298 79,866 107,538 131,324 160,020 204,552 292,288 369,164 451,269 565,431 658,314 826,353 1,025,460 1,407,636 1,691,906 2,151,765 2,306,609 Available Routing Sites(2) 6,216 19,600 32,890 49,600 75,042 92,840 112,530 141,984 191,180 250,142 304,800 389,624 556,740 757,260 925,680 1,159,860 1,462,920 1,836,340 2,278,802 3,128,080 4,101,592 5,216,400 6,150,958 Max Pad Count 44 68 84 100 120 132 144 160 184 208 228 256 304 352 388 432 484 540 600 700 800 900 976 Max I/O Count 36 60 76 92 112 124 136 152 176 200 220 240 288 336 372 416 468 516 576 676 776 876 952 Gate Speed(3) 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps
Rev. 0802E-10/99
1. One gate = NAN2 2. Routing site = 4 transistors 3. Nominal 2-input NAND gate FO = 2 at 3.3V
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Design
Design Systems Supported
Atmel supports several major software systems for design with complete cell libraries, as well as utilities for netlist The following design systems are supported:
System Version 4.4.3 2.1.p2 4.1-s051 2.5 3.4B 2.3 5.2e B2 and Later 98.08, 98.05 SynopsysTM 5.0.1A Exemplar Syntest
TM
verification, test vector verification and accurate delay simulations.
Tools OpusTM - Schematic and Layout NC VerilogTM - Verilog Simulator PearlTM - Static Path Verilog-XLTM - Verilog Simulator Logic Design PlannerTM - Floorplanner BuildGatesTM - Synthesis (Ambit) Modelsim Verilog and VHDL (VITAL) Simulator QuickVHDLTM VSSTM - VHDL Simulator Design CompilerTM - Synthesis Test CompilerTM - Scan Insertion and ATPG PrimetimeTM - Static Path VCSTM - Verilog Simulator Leonardo SpectrumTM - Synthesis TurboCheck - Gate TurboScan TurboFault
Cadence(R)
Mentor/Model TechTM
1998.2f V2.2 V2.2 V1.6
Design Flow and Tools
Atmel's Gate Array/Embedded Array design flow is structured to allow the designer to consolidate the greatest number of system components onto the same silicon chip, using widely available third party design tools. Atmel's cell library reflects silicon performance over extremes of temperature, voltage and process, and includes the effects of metal loading, inter-level capacitance and edge rise and fall times. The design flow includes clock tree synthesis to customer-specified skew and latency goals. RC extraction is performed on the final design database and incorporated into the timing analysis. The Gate Array/Embedded Array Design Flow, shown on the following page, provides a pictorial description of the typical interaction between Atmel's design staff and the customer. Atmel will deliver design kits to support the customer's synthesis, verification, floorplanning and scan insertion activities. Tools such as SynopsysTM, Cadence(R), Verilog-HDL TM , CTgen TM , Exemplar TM , PathMILL TM and TimeMILL TM are used, and many others are available. Should a design include embedded memory (SRAM or ROM) or an embedded core, Atmel will conduct a design review with the customer to understand the partition of the Gate Array/Embedded Array and to define the location of the memory blocks and/or cores so that an underlayer layout model can be created. Following Database Acceptance, automated test pattern generation (ATPG) is performed, if required, on scan paths using Synopsys or SunriseTM tools, the design is routed, and post-route RC data is extracted. After post-route verification and a Final Design Review, the design is taped out for fabrication.
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ATL35 Series
ATL35 Series
Gate Array/Embedded Array Design Flow
Deliver Design Kit
Kickoff Meeting
If Embedded Array
Define Underlayer
Synthesis/ Translation/ Conversion
Scan/JTAG
Simulation/ Static Path
Floorplan
If Embedded Array
Create Underlayer
Database Handoff
Tape Out Underlayer
Database Acceptance
Fabricate Underlayer
Place and Route/ Clock Tree
Verification/ Resimulation
Final Design Review
Tape Out Personality Layers
Fabricate Personality Customer Atmel Joint DVS Assembly and Test
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Pin Definition Requirements
The corner pads are reserved for Power and Ground only. All other pads are fully programmable as Input, Output, Bidirectional, Power or Ground. When implementing a design with 5V compliant buffers, one buffer site must be reserved for the VDD5 pin, which is used to distribute 5V power to the compliant buffers.
Design Options
Logic Synthesis
Atmel can accept netlists in VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-HDL format. Atmel fully supports Synopsys for VHDL TM simulation as well as synthesis. VHDL or Verilog-HDL is Atmel's preferred database format for Gate Array/Embedded Array design.
Gate Array ASIC Design Translation
Atmel has successfully translated existing designs from most major ASIC vendors (LSI Logic(R), Motorola(R), SMOSTM, Oki(R), NEC(R), Fujitsu(R), AMI(R) and others) into Atmel ASICs. These designs have been optimized for speed and gate count and modified to add logic or memory, or replicated as a pin-for-pin compatible, drop-in replacement.
FPGA and PLD Conversions
Atmel has successfully translated existing FPGA/PLD designs from most major vendors (Xilinx(R), Actel(R), Altera(R), AMD (R) and Atmel) into Atmel ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC. Conversion of high volume devices for a single or combined design is cost effective. Performance can often be optimized for speed or low power consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing on-board space requirements. Finally, in situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may provide a lower cost answer for long-term volume production.
Embedded Array
4
ATL35 Series
ATL35 Series
Macro Cores
AVR (8-bit RISC) Microcontroller (8515)
The AVR RISC microcontroller is a true 8-bit RISC ar c hi te c tur e , i d eal l y s ui te d for em be dd ed c on tr ol applications. The AVR is offered as a gate level, soft macro in the ATL35 family. The AVR supports a powerful set of 120 instructions. The AVR pre-fetches an instruction during prior instruction execution, enabling the execution of one instruction per clock cycle. The Fast Access RISC register file consists of 32 general purpose working registers. These 32 registers eliminate the data transfer delay in the traditional program code intensive accumulator architectures. The AVR can incorporate up to 8K x 8 program memory (ROM) and 64K x 8 data memory (SRAM). Also included are several optional peripherals: UART, 8-bit timer/counter, 16-bit timer/counter, external and internal interrupts and programmable watchdog timer.
AVR (8-bit RISC) ASIC Core
ARM7TDMI Embedded Microcontroller Core
The ARM7TDMI is a powerful 32-bit processor offered as an embedded core in the ATL35 series arrays. The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance for very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is
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being decoded, and a third instruction is being fetched from memory. The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these
control signals facilitate the exploitation of the fast local access modes offered by industry standard SRAMs. The ARM7TDMI core includes several optional peripheral macros. The options offered are Real-time Clock, DMA Controller, USART, External Bus Interface, Interrupt, Timer and Advanced Power Management and Controller.
ARM7TDMI Embedded Microcontroller Core
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ATL35 Series
ATL35 Series
OakDSPCore
Atmel's embedded OakDSPCore is a 16-bit, general purpose, low-power, low-voltage and high-speed Digital Signal Processor (DSP). OAK is designed for mid-to-high-end telecommunications and consumer electronics applications, where low-power and portability are major requirements. Among the applications supported are digital cellular telephones, fast modems, advanced facsimile machines and hard disk drives. Oak is available as a DSP core in Atmel's Gate Array cell library, to be utilized as an engine for DSP-based Gate Array/Embedded Array. It is specified with several levels of modularity in SRAM, ROM, I/O blocks, allowing efficient DSP-based Gate Array/Embedded Array development. OAK is aimed at achieving the best cost-performance factor for a given (small) silicon area. As a key element of a system-on-chip, it takes into account such requirements as program size, data memory size, glue logic and power management. The Oak core consists of three main execution units operating in parallel: the Computation/Bit-Manipulation Unit (CBU), the Data Addressing Arithmetic Unit (DAAU) and the Program Control Unit (PCU). The Core also contains ROM and SRAM addressing units, and Program Control Logic (PCL). All other peripheral blocks, which are application specific, are defined as part of the user-specific logic and implemented around the DSP core on the same silicon die. Oak has an enhanced set of DSP and general microprocessor functions to meet most application r e q u i r e m e n ts . T h e O A K p r o g r a m m i n g m o d e l a n d instruction set are aimed at straightforward generation of efficient and compact code.
LodeDSPCore
The LodeDSPCore will be offered in the ATL35 series arrays as an embedded core. Lode is an advanced, 16-bit Digital Signal Processor (DSP) core designed for optimal pe rfo rm anc e in di gi tal c ell ul ar , s pe ec h a nd vo ic e communications applications. The Lode core architecture efficiently performs the baseband functions - speech compression, forward error correction, and modem functions - required by digital cellular standards. Lode is the first general-purpose DSP that provides two multiplier-accumulators (MACs) that reduce power consumption by effectively cutting cycle times in half. Lode's suite of user-friendly development tools are easy to learn, thus accelerating the time it takes to get your product to market.
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ATL35 Series Cell Library
Atmel's ATL35 Series gate arrays make use of an extensive library of cell structures, including logic cells, buffers and inverters, multiplexers, decoders, and I/O options. Soft macros are also available. The ATL35 Series PLL operates at frequencies of up to 250 MHz with minimal phase error and jitter, making it ideal for frequency synthesis of high speed on-chip clocks and chip to chip synchronization. Output buffers are programmable to meet the voltage and current requirements of PCI (20 mA). These cells are characterized by use of SPICE modeling at the tr a nsi s tor l ev el , w ith pe rf or man ce v er i fie d o n manufactured test arrays. Characterization is performed over the rated temperature and voltage ranges to ensure that the simulation accurately predicts the performance of the finished product.
Cell Index
Cell Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI222 AOI2223 AOI2223H AOI222H AOI22H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF8 BUF12 BUF16 CLA7X DEC4 DEC4N DEC8N Description 1-bit Full Adder with Buffered Outputs 2-input AND 2-input AND - High-drive 3-input AND 3-input AND - High-drive 4-input AND 4-input AND - High-drive 5-input AND 2-input AND into 2-input NOR Two, 2-input ANDs into 2-input NOR Three, 2-input ANDs into 3-input NOR Three, 2-input ANDs into 3-input NOR - High-drive Two, 2-input ANDs into 2-input NOR - High-drive 2-input AND into 2-input NOR - High-drive 2-input AND into 3-input NOR 1x Buffer 2x Buffer 2x Tri-state Bus Driver with Active-high Enable 2x Tri-state Bus Driver with Active-low Enable 3x Buffer 4x Buffer 8x Buffer 12x Buffer 16x Buffer 7-input Carry Lookahead 2:4 Decoder 2:4 Decoder with Active-low Enable 3:8 Decoder with Active-low Enable Gate Count 10 2 3 3 4 3 4 5 2 2 4 8 4 4 3 2 2 4 4 3 3 5 8 10 5 8 10 22
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ATL35 Series
ATL35 Series
Cell Index (Continued)
Cell Name DFF DFFBCPX DFFBSRX DFFC DFFR DFFRQ DFFS DFFSR DLY1 DLY2 DLY3 DLY4 DSS DSSBCPY DSSBR DSSBS DSSR DSSS DSSSR HLD1 INV1 INV1D INV1Q INV1TQ INV2 INV2T INV3 INV4 INV8 INV10 JKF JKFBCPX JKFC LAT Description D Flip-flop D Flip-flop with Asynchronous Clear and Preset with Complementary Outputs D Flip-flop with Asynchronous Set and Reset with Complementary Outputs D Flip-flop with Asynchronous Clear D Flip-flop with Asynchronous Reset Quad D Flip-flop with Asynchronous Reset D Flip-flop with Asynchronous Set D Flip-flop with Asynchronous Set and Reset Delay Buffer 1.0 ns Delay Buffer 1.5 ns Delay Buffer 2.0 ns Delay Buffer 4.5 ns Set scan Flip-flop Set scan Flip-flop with Clear and Preset Set scan Flip-flop with Reset Set scan Flip-flop with Set Set scan D Flip-flop with Reset Set scan D Flip-flop with Set Set scan D Flip-flop with Set and Reset Bus Hold Cell 1x Inverter Dual 1x Inverter Quad 1x Inverter Quad 1x Tri-state Inverter with Active-high Enable 2x Inverter 2x Tri-state Inverter with Active-high Enable 3x Inverter 4x Inverter 8x Inverter 10x Inverter JK Flip-flop Clear Preset JK Flip-flop with Asynchronous Clear and Preset and Complementary Outputs JK Flip-flop with Asynchronous Clear LATCH Gate Count 8 16 16 9 10 40 9 11 7 9 11 20 12 16 14 14 12 14 16 4 1 2 4 8 1 3 2 2 4 8 10 16 12 6
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Cell Index (Continued)
Cell Name LATBG LATBH LATR LATS LATSR MUX2 MUX2H MUX2I MUX2IH MUX2N MUX2NQ MUX2Q MUX3I MUX3IH MUX4 MUX4X MUX4XH MUX5H MUX8 MUX8N MUX8XH NAN2 NAN2D NAN2H NAN3 NAN3H NAN4 NAN4H NAN5 NAN5H NAN5S NAN6 NAN6H NAN8 NAN8H NOR2 Description LATCH with Complementary Outputs and Inverted Gate Signal LATCH with High-drive Complementary Outputs LATCH with Reset LATCH with Set LATCH with Set and Reset 2:1 MUX 2:1 MUX - High-drive 2:1 MUX with Inverted Output 2:1 MUX with Inverted Output - High-drive 2:1 MUX with Active-low Enable Quad 2:1 MUX with Active-low Enable Quad 2:1 MUX 3:1 MUX with Inverted Output 3:1 MUX with Inverted Output - High-drive 4:1 MUX 4:1 MUX with Transmission Gate Data Inputs 4:1 MUX with Transmission Gate Data Inputs - High-drive 5:1 MUX - High-drive 8:1 MUX 8:1 MUX with Active-low Enable 8:1 MUX with Transmission Gate Data Inputs - High-drive 2-input NAND Dual 2-input NAND 2-input NAND - High-drive 3-input NAND 3-input NAND - High-drive 4-input NAND 4-input NAND - High-drive 5-input NAND 5-input NAND - High-drive 5-input NAND with Set 6-input NAND 6-input NAND - High-drive 8-input NAND 8-input NAND - High-drive 2-input NOR Gate Count 6 7 5 6 8 4 5 3 4 5 18 16 6 8 10 9 10 14 20 20 16 2 3 2 2 3 3 4 5 6 3 6 7 7 8 2
10
ATL35 Series
ATL35 Series
Cell Index (Continued)
Cell Name NOR2D NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 NOR5S NOR8 OAI22 OAI222 OAI22224 OAI222H OAI22H OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H Description Dual 2-input NOR 2-input NOR - High-drive 3-input NOR 3-input NOR - High-drive 4-input NOR 4-input NOR - High-drive 5-input NOR 5-input NOR with Set 8-input NOR 2-input OR into 2-input NAND Two, 2-input ORs into 2-input NAND Four, 2-input ORs into 4-input NAND Two, 2-input ORs into 2-input NAND - High-drive 2-input OR into 2-input NAND - High-drive 2-input OR into 3-input NAND 2-input OR 2-input OR - High-drive 3-input OR 3-input OR - High-drive 4-input OR 4-input OR - High-drive 5-input OR 2-input Exclusive NOR 2-input Exclusive NOR - High-drive 2-input Exclusive OR 2-input Exclusive OR - High-drive Gate Count 3 2 2 3 3 5 5 3 7 2 3 8 6 4 3 2 3 3 4 3 4 5 4 4 4 4
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3.3 Volt I/O Buffer Cell Index
Cell Name PFIPCI PFPECLL PFPECLR PIC PICH PICI PICS PICSI PID PO11 PO11F PO11S PO22 PO22F PO22I PO22S PO33 PO33F PO33S PO44 PO44F PO44S PO55 PO55F PO55S Description PCI Input Positive ECL Output Positive ECL Output CMOS Input CMOS Input - High-drive CMOS Inverting Input CMOS Input with Schmitt Trigger CMOS Inverting Input with Schmitt Trigger Differential Input 2 mA Tri-state Output 2 mA Tri-state Output (fast) 2 mA Tri-state Output (slow) 4 mA Tri-state Output 4 mA Tri-state Output (fast) 4 mA Inverting Tri-state Output 4 mA Tri-state Output (slow) 6 mA Tri-state Output 6 mA Tri-state Output (fast) 6 mA Tri-state Output (slow) 8 mA Tri-state Output 8 mA Tri-state Output (fast) 8 mA Tri-state Output (slow) 10 mA Tri-state Output 10 mA Tri-state Output (fast) 10 mA Tri-state Output (slow)
3.3 Volt I/O Buffer Cell Index
Cell Name PO66 PO66F PO66S PO77 PO77F PO77S PO88 PO88F PO88S PO99 PO99F PO99S POAA POAAF POAAS POBB POBBF POBBS POCC POCCF POCCS PX1L PX2L PX3L PX4L Description 12 mA Tri-state Output 12 mA Tri-state Output (fast) 12 mA Tri-state Output (slow) 14 mA Tri-state Output 14 mA Tri-state Output (fast) 14 mA Tri-state Output (slow) 16 mA Tri-state Output 16 mA Tri-state Output (fast) 16 mA Tri-state Output (slow) 18 mA Tri-state Output 18 mA Tri-state Output (fast) 18 mA Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) XTAL Oscillator XTAL Oscillator XTAL Oscillator XTAL Oscillator
12
ATL35 Series
ATL35 Series
5.0 Volt Tolerant(1)
Cell Name PFIPCI PFIPCIV PIC PICH PICI PICS PICSI PICSV PICV PO11 PO11F PO11S PO11V PO11VF PO11VS PO22 PO22F PO22I PO22S PO22V PO22VF PO22VS PO33 PO33F PO33S PO33V PO33VF PO33VS PO44 PO44F PO44S PO44V PO44VF PO44VS PO55 PO55F Description PCI Input 5V Tolerant PCI Input CMOS Input CMOS Input - High-drive CMOS Inverting Input CMOS Input with Schmitt Trigger CMOS Inverting Input with Schmitt Trigger 5V Tolerant CMOS Input with Schmitt Trigger 5V Tolerant CMOS Input 2 mA Tri-state Output 2 mA Tri-state Output (fast) 2 mA Tri-state Output (slow) 5V Tolerant 2 mA Tri-state Output 5V Tolerant 2 mA Tri-state Output (fast) 5V Tolerant 2 mA Tri-state Output (slow) 4 mA Tri-state Output 4 mA Tri-state Output (fast) 4 mA Inverting Tri-state Output 4 mA Tri-state Output (slow) 5V Tolerant 4 mA Tri-state Output 5V Tolerant 4 mA Tri-state Output (fast) 5V Tolerant 4 mA Tri-state Output (slow) 6 mA Tri-state Output 6 mA Tri-state Output (fast) 6 mA Tri-state Output (slow) 5V Tolerant 6 mA Tri-state Output 5V Tolerant 6 mA Tri-state Output (fast) 5V Tolerant 6 mA Tri-state Output (slow) 8 mA Tri-state Output 8 mA Tri-state Output (fast) 8 mA Tri-state Output (slow) 5V Tolerant 8 mA Tri-state Output 5V Tolerant 8 mA Tri-state Output (fast) 5V Tolerant 8 mA Tri-state Output (slow) 10 mA Tri-state Output 10 mA Tri-state Output (fast)
5.0 Volt Tolerant(1)
Cell Name PO55S PO55V PO55VF PO55VS PO66 PO66F PO66S PO66V PO66VF PO66VS PO77 PO77F PO77S PO77V PO77VF PO77VS PO88 PO88F PO88S PO88V PO88VF PO88VS PO99 PO99F PO99S PO99V PO99VF PO99VS POAA POAAF POAAS POAAV POAAVF POAAVS POBB POBBF Description 10 mA Tri-state Output (slow) 5V Tolerant 10 mA Tri-state Output 5V Tolerant 10 mA Tri-state Output (fast) 5V Tolerant 10 mA Tri-state Output (slow) 12 mA Tri-state Output 12 mA Tri-state Output (fast) 12 mA Tri-state Output (slow) 5V Tolerant 12 mA Tri-state Output 5V Tolerant 12 mA Tri-state Output (fast) 5V Tolerant 12 mA Tri-state Output (slow) 14 mA Tri-state Output 14 mA Tri-state Output (fast) 14 mA Tri-state Output (slow) 5V Tolerant 14 mA Tri-state Output 5V Tolerant 14 mA Tri-state Output (fast) 5V Tolerant 14 mA Tri-state Output (slow) 16 mA Tri-state Output 16 mA Tri-state Output (fast) 16 mA Tri-state Output (slow) 5V Tolerant 16 mA Tri-state Output 5V Tolerant 16 mA Tri-state Output (fast) 5V Tolerant 16 mA Tri-state Output (slow) 18 mA Tri-state Output 18 mA Tri-state Output (fast) 18 mA Tri-state Output (slow) 5V Tolerant 18 mA Tri-state Output 5V Tolerant 18 mA Tri-state Output (fast) 5V Tolerant 18 mA Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) 5V Tolerant mA Tri-state Output 5V Tolerant mA Tri-state Output (fast) 5V Tolerant mA Tri-state Output (slow) Tri-state Output Tri-state Output (fast)
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5.0 Volt Tolerant(1)
Cell Name POBBS POBBV POBBVF POBBVS POCC POCCF POCCS PX1L PX2L PX3L PX4L Description Tri-state Output (slow) 5V Tolerant mA Tri-state Output 5V Tolerant mA Tri-state Output (fast) 5V Tolerant mA Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) XTAL Oscillator XTAL Oscillator XTAL Oscillator XTAL Oscillator
5.0 Volt Compliant(2)
Cell Name PICV5 PO22V5 PO44V5 Notes: Description 5V Compliant 5V Compliant 4 mA Tri-state Output 5V Compliant 8 mA Tri-state Output
1. Tolerant: Can accept a 5.0 volt input but uses 3.3 volt power supply. 2. Compliant: Can accept a 5.0 volt input or output. Requires a 5.0 volt power supply.
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ATL35 Series
ATL35 Series
Absolute Maximum Ratings*
Operating Ambient Temperature................................................... -55C to +125C Storage Temperature ..................................... -65C to +150C Maximum Input Voltage: Inputs .......................................................................VDD + 0.5V 5V Tolerant/Compliant ........................................... VDD5 + 0.5V Maximum Operating Voltage (VDD) ................................... 3.6V Maximum Operating Voltage (VDD5 ) ................................. 5.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.5 Volt DC Characteristics
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol TA VDD IIH IIL IOZ IOS Parameter Operating Temperature Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Output Short-circuit Current High-level Input Voltage Buffer All All CMOS PCI CMOS PCI All PO11 PO11 CMOS VIH PCI CMOS Schmitt CMOS VIL VHYS VOH VOL Low-level Input Voltage Hysteresis High-level Output Voltage Low-level Output Voltage PCI CMOS Schmitt CMOS Schmitt PO11 PCI PO11 PCI IOH = 1.4 mA, VDD = VDD (min) IOH = -500 A IOL = 1.4 mA, VDD = VDD (min) IOL = 1.5 mA 0.7VDD 0.9VDD 0.4 0.1VDD 1.0 0.5 VIN = VDD or VSS, VDD = VDD (max), No pull-up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD = VDD (max) 0.7VDD 0.475VDD 0.7VDD 1.5 0.3VDD 0.325VDD 0.3VDD V V V V V VIN = VSS, VDD = VDD (max) -10 -10 -10 9 6 10 VIN = VDD, VDD = VDD (max) Test Condition Min -55 2.3 2.5 Typ Max 125 2.7 10 10 Units C V A A A mA
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3.3 Volt DC Characteristics
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol TA VDD IIH IIL IOZ IOS Parameter Operating Temperature Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Output Short-circuit Current Buffer All All CMOS PCI CMOS PCI All PO11 PO11 CMOS, LVTTL VIH High-level Input Voltage PCI CMOS/TTL-level Schmitt CMOS VIL Low-level Input Voltage PCI CMOS/TTL-level Schmitt Hysteresis High-level Output Voltage Low-level Output Voltage TTL-level Schmitt PO11 PCI PO11 PCI IOH = 2 mA, VDD = VDD (min) IOH = -500 A IOL = 2 mA, VDD = VDD (min) IOL = 1.5 mA 0.7VDD 0.9VDD 0.4 0.1VDD 1.1 0.6 VIN = VDD or VSS, VDD = VDD (max), No pull-up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD = VDD (max) 2.0 0.475VDD 2.0 1.7 0.8 0.325VDD 0.8 V V V V V VIN = VSS, VDD = VDD (max) -10 -10 -10 14 -9 10 VIN = VDD, VDD = VDD (max) Test Condition Min -55 3.0 3.3 Typ Max 125 3.6 10 10 Units C V A A A mA
VHYS VOH VOL
16
ATL35 Series
ATL35 Series
5.0 Volt DC Characteristics
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol TA VDD VDD5 IIH IIL IOZ IOS Parameter Operating Temperature Supply Voltage Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Output Short-circuit Current Buffer All 5V Tolerant 5V Compliant CMOS CMOS All PO11V PO11V PICV, PICV5 VIH High-level Input Voltage PCI CMOS/TTL-level Schmitt PICV, PICV5 VIL Low-level Input Voltage PCI CMOS/TTL-level Schmitt Hysteresis High-level Output Voltage Low-level Output Voltage CMOS/TTL-level Schmitt PO11V PO11V5 PO11V, PO11V5 IOH = -1.7 mA IOH = -1.7 mA IOL = 1.7 mA 0.7VDD 0.7VDD5 0.5 1.1 0.6 VIN = VDD, VDD = VDD (max) VIN = VSS, VDD = VDD (max) VIN = VDD or VSS, VDD = VDD (max), No pull up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD = VDD (max) 2.0 0.475VDD 2.0 -10 -10 8 -7 5.0 5.0 1.7 0.5VDD 0.8 0.325VDD 0.8 V V V V 5.5 5.5 V 10 Test Condition Min -55 3.0 4.5 Typ 3.3 5.0 Max 125 3.6 5.5 10 Units C V V A A A
mA
VHYS VOH VOL
I/O Buffer DC Characteristics
Symbol CIN COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bidirectional Test Condition 3.3V 3.3V 3.3V Typical 2.4 5.6 6.6 Units pF pF pF
Testability Techniques
For complex designs, involving blocks of memory and/or cores, careful attention must be given to design-for-test techniques. The sheer size of complex designs and the number of functional vectors that would need to be created to exercise them fully, strongly suggests the use of more efficient techniques. Combinations of SCAN paths, multiplexed access to memory and/or core blocks, and built-inself-test logic must be employed, in addition to functional test patterns, to provide both the user and Atmel the ability to test the finished product. An example of a highly complex design could include a PLL for clock management or synthesis, a microcontroller or DSP engine or both, SRAM to support the microcontroller or DSP engine, and glue logic to support the interconnectivity of each of these blocks. The design of each of these blocks must take into consideration the fact that the manufactured device will be tested on a high performance digital tester. Combinations of parametric, functional, and structural tests, defined for digital testers, should be employed to create a suite of manufacturing tests. The type of block dictates the type of testability technique to be employed. The PLL will, by construction, provide access to key nodes so that functional and / or parametric testing can be performed. Since a digital tester must control 17
all the clocks during the testing of a Gate Array/Embedded Arr ay, pr ovisi on must be made for the VCO to be bypassed. Atmel's PLLs include a multiplexing capability for just this purpose. The addition of a few pins will allow other portions of the PLL to be isolated for test, without impinging upon the normal functionality. In a similar vein, access to microcontroller, DSP and SRAM blocks must be provided so that controllability and observability of the inputs and outputs to the blocks are achieved with the minimum amount of preconditioning. The AVR and ARM microcontrollers support SCAN testing, as do the three main execution units of the OakDSP. SRAM and CAM blocks need to provide access to both address and data ports so that comprehensive memory tests can be performed. Multiplexing I/O pins provides a method for providing this accessibility. The glue logic can be designed using full SCAN techniques to enhance its testability. It should be noted that, in almost all of these cases, the purpose of the testability technique is to provide Atmel a means to assess the structural integrity of a Gate Array/Embedded Array; i.e., sort devices with manufactur-
ing-induced defects. All of the techniques described above should be considered supplemental to a set of patterns which exercise the functionality of the design in its anticipated operating modes.
Advanced Packaging
The ATL35 Series gate arrays are offered in a wide variety of standard packages, including plastic and ceramic quad flatpacks, thin quad flatpacks, ceramic pin grid arrays, and ball grid arrays. High volume onshore and offshore contractors provide assembly and test for commercial product, with prototype capability in Colorado Springs. Custom package designs are also available as required to meet a customer's specific needs, and are supported through Atmel's package design center. When a standard package cannot meet a customer's need, a package can be designed to precisely fit the application and to maintain the performance obtained in silicon. Atmel has delivered custom-designed packages in a wide variety of configurations.
Packaging Options
Package Type PQFP Power Quad L/TQFP PLCC CPGA CQFP PBGA Super BGA Low-profile Mini BGA Chip-scale BGA Note:
(1)
Pin Count 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304 144, 160, 208, 240, 304 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216 20, 28, 32, 44, 52, 68, 84 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391 64, 68, 84, 100, 120, 132, 144, 160, 224, 340 121, 169, 208, 217, 225, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 456 168, 204, 240, 256, 304, 352, 432, 560, 600 132, 144, 160, 180, 208 40, 49, 56, 64, 81, 84, 96, 100, 128
1. Partial list
18
ATL35 Series
Atmel Headquarters
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Fax-on-Demand
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e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
(c) Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing
(R)
and/or
TM
are registered trademarks and trademarks of Atmel Corporation. Printed on recycled paper.
0802E-10/99/0M
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